As technology advances, new semiconductor memory devices have been required to store more information and to communicate that information more quickly. A dual-port memory structure is one such memory device that provides data in an efficient manner desired by current data processing systems. In a dual port memory, two polts are implemented so that the contents of the memory may be concurrently accessed from two different sources. An example of such a dual port memory is illustrated in FIG. 1.
In the dual port memory cell of FIG. 1, transistors 106, 108, 110, and 112 form a latch for storing data within the memory cell. In contrast, transistors 104, 102, 114, and 116 are pass devices that allow data to be stored within and read from the memory cell. Through the selective enabling of the "latch" transistor and the "pass" transistors, data is stored within and read from the dual-port memory cell.
In such a dual port memory cell, two pass devices can potentially be driving concurrently current to a node (such as node N.sub.0). In this case, where two pass devices 114 and 116 are coupled at the node N.sub.0 to the memory cell latch devices 106/108, a beta ratio between the pass devices and the NFET latch devices must be increased by a factor of two, since there will be twice as much current to the node through the two pass devices than there would be through a single pass device. This increased beta ratio is reflected in increased circuit area requirements which, in turn, increase the costs associated with manufacturing the circuit. The issue of increasing current due to increasing number of ports is described, for example, in U.S. Pat. No. 5,657,291 to Podlesny, et al., "Multi-Port Register File Memory Cell Configuration for Read Operations, at c.2, 11. 25f.
Therefore, a need exists for an apparatus and method for accessing dual port memories which reduces an amount of circuit area requirements, while maintaining the functionality typically associated with such dual port memories.